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Features
* maXTouchTM Touchscreen
- True 12-bit multi-touch with independent XY tracking for up to 10 concurrent touches in real time with touch size reporting - Up to 4.3 inch diagonal screen size supported with 10 mm "pinch" separation - Up to 10.1 inch support with correspondingly wider "pinch" Number of Channels - Up to 224 (subject to other configuration limitations) - Electrode grid configurations up to 20 X by 10 Y lines supported (subject to 30 total pins and a maximum of 14 Y lines) maXTouch Touch Key Support - Up to 32 channels can be allocated as fixed keys (subject to other configurations) Zero Additional Part Count - 16 X by 14 Y matrix (224 channels) implementable with power bypass capacitors only Signal Processing - Advanced digital filtering using both hardware engine and firmware - Self-calibration - Auto drift compensation - Adjacent Key Suppression(R) (AKSTM) technology - Grip and face suppression - Reports one-touch and two-touch gestures - Down-scaling and clipping support to match LCD resolution - Ultra-fast start-up and calibration for best user experience - Supports axis flipping and axis switch-over for portrait and landscape modes Scan Speed - Maximum single touch >250Hz, subject to configuration - Configurable to allow power/speed optimization - Programmable timeout for automatic transition from active to idle states Response Times - Initial latency <10 ms for first touch from idle, subject to configuration Sensors - Works with PET or glass sensors - Works with all proprietary sensor patterns recommended by Atmel(R) - Works with passive stylus Panel Thickness - Glass up to 3 mm, screen size dependent - Plastic up to 1.5 mm, screen size dependent Interface - I2C-compatible slave mode 400 kHz Dual-rail Power - Interface 1.8V to 3.3V nominal, analog 2.7V to 3.3V nominal Power Consumption - Idle 80Hz: <1.8 mW, subject to configuration - One Touch Active 80Hz: 3.9 mW, subject to configuration - Sleep: 4.5 W Package - 49-ball UFBGA 5 x 5 x 0.6 mm, 0.65 ball pitch - 49-ball VFBGA 5 x 5 x 1 mm, 0.65 ball pitch - 48-pin QFN 6 x 6 x 0.6 mm, 0.4 mm pin pitch
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maXTouchTM 224-channel Touchscreen Sensor IC MXT224
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Summary
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Note: This is a summary document. A complete document is available under NDA. For more information contact www.atmel.com/touchscreen.
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9530BS-AT42-10/09
1. Pinout and Schematic
1.1
1.1.1
Pinout Configuration
49-ball UFBGA/VFBGA
Top View
1 A B C D E F G 2 3 4 5 6 7 7 6
Bottom View
5 4 3 2 1 A B C
QT602240
MXT224
D E F G
1.1.2
48-pin QFN
Y10 Y12 1 2 3 4 5 6 7 8 9 10 11 Y11 Y7 Y4 Y3 Y6 Y5 Y8 Y9 Y2 Y1
Y13 GND AVDD X8 X9 X10 X11 X12 X13 X14 X15 GND
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
Y0 GND AVDD X7 X6 X5 X4 X3 X2 X1 X0 GND
MXT224
25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD RESET N/C SDA SCL GPIO0/SYNC GPIO1 VDD GPIO2/SCK GPIO3/MOSI ADDR_SEL CHG
2
MXT224
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MXT224
1.2
1.2.1 Table 1-1.
Ball A1 A2 A3 A4 A5 A6 A7 B1 B2 B3 B4 B5 B6 B7 C1 C2 C3 C4 C5 C6 C7 D1 D2 D3 D4 D5 D6 D7 E1 E2 E3 E4
Pinout Descriptions
49-ball UFBGA/VFBGA Pin Listing
Name AVDD Y12 Y10 Y8 Y6 Y4 Y2 X8 GND Y11 Y9 Y5 Y1 Y0 X10 X9 Y13 Y7 Y3 GND AVDD X12 X13 X11 GND X7 X5 X6 X14 X15 RESET GPIO1 Type P I/O I/O I I I I O P I/O I I I I O O I/O I I P P O O O P O O O O O I I/O Comments Analog power Y line connection or X line in extended mode Y line connection or X line in extended mode Y line connection Y line connection Y line connection Y line connection X matrix drive line Ground Y line connection or X line in extended mode Y line connection Y line connection Y line connection Y line connection X matrix drive line X matrix drive line Y line connection or X line in extended mode Y line connection Y line connection Ground Analog power X matrix drive line X matrix drive line X matrix drive line Ground X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line Reset low; has internal 30 k to 60 k pull-up resistor General purpose I/O If Unused, Connect To... - Leave open Leave open Leave open Leave open Leave open Leave open Leave open - Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open - - Leave open Leave open Leave open - Leave open Leave open Leave open Leave open Leave open Leave open or Vdd Input: GND Output: leave open
3
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Table 1-1.
Ball E5 E6 E7 F1 F2 F3 F4 F5 F6 F7 G1 G2 G3 G4 G5 G6 G7 I O P
Pin Listing (Continued)
Name X1 X3 X4 VDD GND SCL GPIO3/ MOSI GND CHG X2 N/C SDA GPIO0/ SYNC GPIO2/ SCK VDD ADDR_SEL X0 Type O O O P P OD I/O P OD O - OD I/O I/O P I O Comments X matrix drive line X matrix drive line X matrix drive line Digital power Ground Serial Interface Clock General purpose I/O / Debug data Ground State change interrupt X matrix drive line No connection Serial Interface Data General purpose I/O External synchronization General purpose I/O / Debug clock Digital power I C-compatible address select X matrix drive line I/O OD Input and output Open drain output
2
If Unused, Connect To... Leave open Leave open Leave open - - - Input: GND Output: leave open - - Leave open Leave open - Input: GND Output: leave open Input: GND Output: leave open - - Leave open
Input only Output only, push-pull Ground or power
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MXT224
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MXT224
1.2.2 Table 1-2.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48-pin QFN Pin Listing
Name Y13 GND AVDD X8 X9 X10 X11 X12 X13 X14 X15 GND VDD RESET N/C SDA SCL GPIO0/ SYNC GPIO1 VDD GPIO2/ SCK GPIO3/ MOSI ADDR_SEL CHG GND X0 X1 X2 X3 X4 X5 X6 Type I/O P P O O O O O O O O P P I - OD OD I/O I/O P I/O I/O I OD P O O O O O O O Comments Y line connection or X line in extended mode Ground Analog power X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line Ground Digital power Reset low; has internal 30 k to 60 k pull-up resistor No connection Serial Interface Data Serial Interface Clock General purpose I/O External synchronization General purpose I/O Digital power General purpose I/O / Debug clock General purpose I/O / Debug data I2C-compatible address select State change interrupt Ground X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line X matrix drive line If Unused, Connect To... Leave open - - Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open - - Leave open or Vdd Leave open - - Input: GND Output: leave open Input: GND Output: leave open - Input: GND Output: leave open Input: GND Output: leave open - - - Leave open Leave open Leave open Leave open Leave open Leave open Leave open
5
9530BS-AT42-10/09
Table 1-2.
Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I O P
Pin Listing (Continued)
Name X7 AVDD GND Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Type O P P I I I I I I I I I I I/O I/O I/O Comments X matrix drive line Analog power Ground Y line connection Y line connection Y line connection Y line connection Y line connection Y line connection Y line connection Y line connection Y line connection Y line connection Y line connection or X line in extended mode Y line connection or X line in extended mode Y line connection or X line in extended mode I/O OD Input and output Open drain output If Unused, Connect To... Leave open - - Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open
Input only Output only, push-pull Ground or power
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MXT224
9530BS-AT42-10/09
MXT224
1.3
1.3.1
Schematic
49-ball UFBGA/VFBGA
Regulated Regulated VDD AVDD
NOTE: Bypass capacitors must be X7R or X5R and placed <5 mm away from chip.
100 nF
1 mF
100 nF
1 mF
G5
F1
C7
A1
VDD
AVDD
VDD
E4 G4
VDD
F4
Rp
Rp
G2 F3 G1
I C-COMPATIBLE
2
SDA SCL
VDD
E3
G3
Rc CHG I C-COMPATIBLE ADDRESS SELECT
2
X0 X1 X2 GPIO1 X3 GPIO2/SCK X4 X5 GPIO3/MOSI X6 X7 MXT224 QT602240 X8 X9 X10 X11 SDA X12 SCL X13 X14 N/C X15 RESET X16/Y13 X17/Y12 GPIO0/SYNC X18/Y11 X19/Y10 CHG ADDR_SEL GND GND GND GND GND Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
AVDD
G7 E5 F7 E6 E7 D6 D7 D5 B1 C2 C1 D3 D1 D2 E1 E2 C3 A2 B3 A3 B4
F6 G6 B2 C6 D4 F2 F5
C4 A5 B5 A6 C5 A7 B6 B7
* NOTE: Y10 to Y13 scan lines may be used as additional X drive lines in extended mode (a 100W resistor must be added to each additional line).
MATRIX Y SCAN IN
A4
MATRIX Y OR X*
MATRIX X DRIVE
7
9530BS-AT42-10/09
1.3.2
48-pin QFN
Regulated Regulated VDD AVDD
NOTE: Bypass capacitors must be X7R or X5R and placed <5 mm away from chip.
100 nF
1 mF
100 nF
1 mF
13
20
34
3
VDD
AVDD
VDD
19 21
VDD
22
Rp
Rp
16 17 15
I C-COMPATIBLE
2
SDA SCL
VDD
14
18
Rc CHG I C-COMPATIBLE ADDRESS SELECT
2
X0 X1 X2 GPIO1 X3 GPIO2/SCK X4 X5 GPIO3/MOSI X6 X7 MXT224 QT602240 X8 X9 X10 X11 SDA X12 SCL X13 X14 N/C X15 RESET X16/Y13 X17/Y12 GPIO0/SYNC X18/Y11 X19/Y10 CHG ADDR_SEL Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
AVDD
26 27 28 29 30 31 32 33 4 5 6 7 8 9 10 11 1 48 47 46 45
24 23
43 42 41 40 39 38 37 36
2 12 25 35
GND GND GND GND
* NOTE: Y10 to Y13 scan lines may be used as additional X drive lines in extended mode (a 100W resistor must be added to each additional line).
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MXT224
9530BS-AT42-10/09
MATRIX Y SCAN IN
44
MATRIX Y OR X*
MATRIX X DRIVE
MXT224
2. Overview of the MXT224
2.1 Introduction
The MXT224 (AT42QT602240) uses a unique charge-transfer acquisition engine to implement the QMatrixTM capacitive sensing method patented by Atmel(R). This allows the measurement of up to 224 mutual capacitance nodes in under 1 ms. Coupled with a state-of-the-art XMEGATM CPU, the entire touchscreen sensing solution can measure, classify and track a single finger touch every 4 ms if required. The acquisition engine uses an optimal measurement approach to ensure almost complete immunity from parasitic capacitance on the receiver inputs (Y lines). The engine includes sufficient dynamic range to cope with touchscreen mutual capacitances spanning 0.5 pF to 5 pF, allowing great flexibility for use with Atmel's proprietary ITO pattern designs. One and two layer ITO sensors are possible using glass or PET substrates. The main AVR (R) XMEGA CPU has, under its control, two powerful, yet low power, microsequencer coprocessors. These combine to allow the signal acquisition, preprocessing, postprocessing and housekeeping to be partitioned in an efficient and flexible way. This gives ample scope for sensing algorithms, touch tracking or advanced shape-based filtering. An in-circuit reflash can be performed over the chip's hardware-driven two-wire interface (I2C-compatible). Overall, the MXT224 represents a step improvement over competing technologies, providing a near optimal mix of low power, small size and low part count, while offering unrivalled true multitouch performance.
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9530BS-AT42-10/09
Revision History
Revision Number Revision AS - September 2009 Revision BS - October 2009 History Initial release for chip revision 1.4 QFN package details added
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MXT224
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MXT224
Notes
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9530BS-AT42-10/09
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Unit 01-05 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Touch Technology Division 1 Mitchell Point Ensign Way Hamble Southampton Hampshire SO31 4RF United Kingdom Tel: (44) 23-8056-5600 Fax: (44) 23-8045-3939 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support touch@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
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(c) 2009 Atmel Corporation. All rights reserved. Atmel(R), Atmel logo and combinations thereof, AVR (R), Adjacent Key Suppression (R) and others are registered trademarks, maXTouchTM, AKS TM, QMatrix TM, XMEGA TM and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be registered trademarks or trademarks of others.
9530BS-AT42-10/09

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